An FPGA based demonstrator for a topological processor in the,future ATLAS L1-Calo trigger (“GOLD”)

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The existing ATLAS trigger consists of three levels. The level 1 (L1) is an FPGAs based custom designed trigger, while the second and third levels are software based. The LHC machine plans to bring the beam energy to the nominal value of 7 TeV and to increase the luminosity in the coming years. The...

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Detalles Bibliográficos
Autores principales: "Bauss, B", "Buescher, V", "Degele, R", "Ebling, A", "Ji, W", "Meyer, C", "Moritz, S", "Schaefer, U", "Simioni, E", "Tapprogge, S", "Wenzel, V"
Lenguaje:eng
Publicado: 2011
Materias:
Detectors and Experimental Techniques
Acceso en línea:http://cds.cern.ch/record/1384801

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