Optimal Filtering Algorithm implementation in FPGAs for the ATLAS TileCal Read-Out Drivers

The Large Hadron Collider (LHC) is a powerful particle accelerator built in Geneva (Switzerland), developed to achieve proton beam collisions at 14 TeV. It comprises four experiments: ALICE, CMS, LHCb and ATLAS, this last one being a general purpose particle detector. The ATLAS Hadronic Tile Calorimeter (TileCal) is one of its sub-systems, which is designed to measure the energy carried by the particles that cross the detector. The Read-Out Driver (ROD) is a key element of the TileCal data acquisition chain. It processes, in real time, the digitized information coming from the front-end electronics and sends it to the Read-Out System. Data processing in the ROD boards is performed in Processing Unit Mezzanine Cards that use commercial DSPs to run the Optimal Filtering (OF) algorithms. Present-day FPGAs contain DSP slices, giving the designers the possibility to implement these algorithms and, at the same time, to exploit the flexibility that these devices provide to easily upgrade the system to new functionalities by modifying only the firmware. The hardware platform to test the implementation of the OF algorithm will be a prototype of a FPGA-based Mezzanine Processing Unit card. It has been designed to be fully compatible with the present-system, but is also suitable for studying the possibilities of providing extended functionalities. First, a functional description of the hardware platform will be given. After that, the main points of the hardware design, the status of the board, as well as the tests being planned to validate the Mezzanine card will be explained. In the third part, the OF algorithm will be briefly described, as well as the principal aspects of the firmware development for its implementation on the FPGA DSP slices. In the last part, some ideas for improving the current functionality of the system will be presented and evaluated.