Design of the ATLAS IBL Readout System

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An Insertable B-Layer is planned for the upgrade of the ATLAS detector and will add a fourth and innermost silicon layer to the existing Pixel Detector. 12 million pixels attached to new FE-I4 readout ASICs will require new off-detector electronics which is currently realized with two VME-based boar...

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Detalles Bibliográficos
Autores principales: Polini, A, Bruni, G, Bruschi, M, D'Antone, I, Dopke, J, Falchieri, D, Flick, T, Gabrielli, A, Grosse-Knetter, J, Joseph, J, Nina Krieger, N, Kugel, A, Morettini, P, Rizzi, M, Schroer, N, Travaglini, R, Zannoli, S, Zoccoli, A
Lenguaje:eng
Publicado: 2011
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1016/j.phpro.2012.02.524
http://cds.cern.ch/record/1393406
Descripción
Sumario:An Insertable B-Layer is planned for the upgrade of the ATLAS detector and will add a fourth and innermost silicon layer to the existing Pixel Detector. 12 million pixels attached to new FE-I4 readout ASICs will require new off-detector electronics which is currently realized with two VME-based boards: a Back Of Crate module implementing optical I/O functionality and a Readout Driver module for data processing. This paper illustrates the new read-out chain, focusing on the design of the new Readout Driver Card, which, with a fourfold integration with respect to the previous design, builds up the detector data, controls the calibration procedures and interacts via Gigabit links with a novel calibration farm. Future prospects and back compatibility to the existing system are also addressed.

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