Associative Memory Design for the Fast TracKer Processor (FTK)at ATLAS

We describe a VLSI processor for pattern recognition based on Content Addressable Memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments. A large CAM bank stores all trajectories of interest and extracts the ones compatible with a given event. This task is naturally parallelized by a CAM architecture able to output identified trajectories, recognized among a huge amount of possible combinations, in just a few 100 MHz clock cycles. We have developed this device (called the AMchip03 processor), using 180 nm technology, for the Silicon Vertex Trigger (SVT) upgrade at CDF [1] using a standard-cell VLSI design methodology. We propose a new design that introduces a full custom CAM cell and takes advantage of 65 nm technology. The customized design maximizes the pattern density, minimizes the power consumption and implements the functionalities needed for the planned Fast Tracker (FTK) [2], an ATLAS trigger upgrade project at LHC. We introduce a new variable resolution pattern matching technique using dont care bits, allowing for a more effective pattern matching by adding 3 dont care bits per layer. Thus, the effective pattern-matching window for each pattern and each layer can be independently increased by a factor 2, 4 or 8 depending on the number of used dont care bits. For the planned application a factor 5 more efficient use of AM patterns is expected, thus saving significant silicon area.