4 Channel Slave Direct-Digital-Synthesizer – SDDS (EDA-00992)

A novel rf beam control architecture has been successfully tested in the LEIR synchrotron. The design is based on a VME 64X carrier board, including a DSP (digital signal processor), into which different daughter cards can be plugged in. The SDDS (Slave Direct Digital Synthesizer) is one of them. Hardware wise it has the features of a four-channel DAC (digital-to-analogue converter) which inputs are driven by a powerful FPGA (field programmable logic array); the latter is connected to the DSP on the carrier board via high-speed connectors. Mainly, this unit will supply the rf signals driving the cavities at a specified harmonic of the revolution. The main sampling clock feeding the mezzanine board is at a high harmonic of the particle’s revolution frequency. In the PSB, this frequency is varying along the accelerating cycle and this choice allows creating the rf signal feeding the accelerating cavities without changing any parameter along the cycle. The sampling clock is tagged at the revolution rate allowing for a synchronous load of new parameters along the accelerating cycle. Synchronous means in phase with the different electronic boards composing the rf beam control. The different signal processing features programmed in the FPGA will be depicted in this note.