The ATLAS IBL BOC Demonstrator

The Insertable-B-Layer (IBL) is a new pixel detector layer to be installed at the ATLAS experiment at the LHC, CERN in 2013. It will be integrated into the general pixel readout and software framework, hence the off-detector readout electronics has to support the new front-end electronics whilst maintaining a high degree of interoperability to the components of the existing system. The off-detector readout is realised using a number of VME card pairs – ROD and BOC – plus a VME crate controller and a custom timing distribution system. The main elements of the new BOC design comprise optical interfaces towards the detector, signal conditioning and data recovery logic. We present the demonstrator used to verify the design approach. The demonstrator is based on a XILINX SP605 FPGA evaluation board and uses a Microblaze processor inside the FPGA to provide easy and flexible access to all essential BOC functions and the corresponding emulator modules, which enable full test of the entire BOC functionality even without any external components. However, optical interfaces may be connected via a mezzanine card. We present the details of the emulation circuitries together with measurement results showing the operation of the BOC logic.