Principles of VLSI RTL design: a practical guide

This book examines the impact of register transfer level (RTL) design choices that may result in issues of testability, data synchronization across clock domains, synthesizability, power consumption and routability, that appear later in the product lifecycle.

Detalles Bibliográficos
Autores principales: Churiwala, Sanjay, Garg, Sapan, Gianfagna, Mike
Lenguaje:eng
Publicado: Springer 2011
Materias:
Engineering
Acceso en línea:http://cds.cern.ch/record/1407179
Descripción
Sumario:This book examines the impact of register transfer level (RTL) design choices that may result in issues of testability, data synchronization across clock domains, synthesizability, power consumption and routability, that appear later in the product lifecycle.

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