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Principles of VLSI RTL design: a practical guide

This book examines the impact of register transfer level (RTL) design choices that may result in issues of testability, data synchronization across clock domains, synthesizability, power consumption and routability, that appear later in the product lifecycle.

Detalles Bibliográficos
Autores principales: Churiwala, Sanjay, Garg, Sapan, Gianfagna, Mike
Lenguaje:eng
Publicado: Springer 2011
Materias:
Acceso en línea:http://cds.cern.ch/record/1407179
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author Churiwala, Sanjay
Garg, Sapan
Gianfagna, Mike
author_facet Churiwala, Sanjay
Garg, Sapan
Gianfagna, Mike
author_sort Churiwala, Sanjay
collection CERN
description This book examines the impact of register transfer level (RTL) design choices that may result in issues of testability, data synchronization across clock domains, synthesizability, power consumption and routability, that appear later in the product lifecycle.
id cern-1407179
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2011
publisher Springer
record_format invenio
spelling cern-14071792021-04-22T00:46:59Zhttp://cds.cern.ch/record/1407179engChuriwala, SanjayGarg, SapanGianfagna, MikePrinciples of VLSI RTL design: a practical guideEngineeringThis book examines the impact of register transfer level (RTL) design choices that may result in issues of testability, data synchronization across clock domains, synthesizability, power consumption and routability, that appear later in the product lifecycle.Springeroai:cds.cern.ch:14071792011
spellingShingle Engineering
Churiwala, Sanjay
Garg, Sapan
Gianfagna, Mike
Principles of VLSI RTL design: a practical guide
title Principles of VLSI RTL design: a practical guide
title_full Principles of VLSI RTL design: a practical guide
title_fullStr Principles of VLSI RTL design: a practical guide
title_full_unstemmed Principles of VLSI RTL design: a practical guide
title_short Principles of VLSI RTL design: a practical guide
title_sort principles of vlsi rtl design: a practical guide
topic Engineering
url http://cds.cern.ch/record/1407179
work_keys_str_mv AT churiwalasanjay principlesofvlsirtldesignapracticalguide
AT gargsapan principlesofvlsirtldesignapracticalguide
AT gianfagnamike principlesofvlsirtldesignapracticalguide