Entwicklung, Implementierung and Test eines FPGA-Designs für die Level-1-Frontend-Elektronik des Äusseren Spurkammersystems im LHCb-Detektor

For measurements of CP-violation in the B-meson system, as well as the search for new physics, the LHCb-experiment has been built at the Large Hadron Collider at CERN. One component of the sophisticated LHCb-detector is the Outer Tracker. Its measured data is transmitted serially via optical links into the readout network. For the interface between the frontend electronics on the detector and the data acquisition network a common readout board is used. This FPGA-based board, dubbed the TELL1, preprocesses the data. In this thesis the developments of the detector specific parts of the TELL1 firmware and the integration of the TELL1 board into the readout chain of the Outer Tracker are described. It covers the synchronisation and the error detection of the data received, as well as the generation of the Outer Tracker DAQ data format. In addition a zero-suppression algorithm has been implemented in the FPGA in order to reduce the network payload and guarantee operation at maximum trigger rate.