Evaluation of 65nm technology for CLIC pixel front-end

The CLIC vertex detector design requires a high single point resolution (~ 3 μm) and a precise time stamp (≤ 10 ns). In order to achieve this spatial resolution, small pixels (in the order of 20 μm pitch) must be used, together with the measurement of the charge deposition of neighbouring channels. Designing such small pixels requires the use of a deep downscaled CMOS technology. This note describes the design and characterisation of suitable building blocks implemented in a commercial 65 nm process. The characterisation included an evaluation of the radiation hardness of the blocks.