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C/VHDL Codesign for LHCb VELO zero suppression algorithms
We present a workflow to generate cycle-accurate C and VHDL code from one common description to accelerate and unify algorithm implementation and simulation for real-time DSP applications in particle detectors. We use Confluence as description language which compiles into C-code (for simulation) an...
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Lenguaje: | eng |
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2005
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Acceso en línea: | http://cds.cern.ch/record/1443519 |
_version_ | 1780924720917512192 |
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author | Muecke, Manfred |
author_facet | Muecke, Manfred |
author_sort | Muecke, Manfred |
collection | CERN |
description | We present a workflow to generate cycle-accurate C and VHDL code from one common description to accelerate and unify algorithm implementation and simulation for real-time DSP applications in particle detectors. We use Confluence as description language which compiles into C-code (for simulation) and VHDL code (for implementation on FPGAs). We demonstrate the improved portability and simulation speed while assuring bit- and cycle-accuracy. Our approach solves the problem of having to maintain two source codes (for simulation and implementation) in parallel and therefore minimizes workload and the danger of inconsistent models. This is crucial in an environment where algorithm implementation is expected to cycle through several design iterations. |
id | cern-1443519 |
institution | Organización Europea para la Investigación Nuclear |
language | eng |
publishDate | 2005 |
record_format | invenio |
spelling | cern-14435192019-09-30T06:29:59Zhttp://cds.cern.ch/record/1443519engMuecke, ManfredC/VHDL Codesign for LHCb VELO zero suppression algorithmsComputing and ComputersWe present a workflow to generate cycle-accurate C and VHDL code from one common description to accelerate and unify algorithm implementation and simulation for real-time DSP applications in particle detectors. We use Confluence as description language which compiles into C-code (for simulation) and VHDL code (for implementation on FPGAs). We demonstrate the improved portability and simulation speed while assuring bit- and cycle-accuracy. Our approach solves the problem of having to maintain two source codes (for simulation and implementation) in parallel and therefore minimizes workload and the danger of inconsistent models. This is crucial in an environment where algorithm implementation is expected to cycle through several design iterations.LHCb-PROC-2005-008CERN-LHCb-PROC-2005-008oai:cds.cern.ch:14435192005-06-04 |
spellingShingle | Computing and Computers Muecke, Manfred C/VHDL Codesign for LHCb VELO zero suppression algorithms |
title | C/VHDL Codesign for LHCb VELO zero suppression algorithms |
title_full | C/VHDL Codesign for LHCb VELO zero suppression algorithms |
title_fullStr | C/VHDL Codesign for LHCb VELO zero suppression algorithms |
title_full_unstemmed | C/VHDL Codesign for LHCb VELO zero suppression algorithms |
title_short | C/VHDL Codesign for LHCb VELO zero suppression algorithms |
title_sort | c/vhdl codesign for lhcb velo zero suppression algorithms |
topic | Computing and Computers |
url | http://cds.cern.ch/record/1443519 |
work_keys_str_mv | AT mueckemanfred cvhdlcodesignforlhcbvelozerosuppressionalgorithms |