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Online tracking applications of the general purpose EDRO Board
The capability to perform extremely fast track reconstruction online is becoming more and more important for the LHC upgrade as well as the next generation of HEP experiments, where the expected instantaneous luminosities (in excess of 10^34 /cm2/s) and the very low signal/background ratio ask for f...
Autores principales: | , , , , , , , , , , , , , , |
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Lenguaje: | eng |
Publicado: |
2012
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Materias: | |
Acceso en línea: | http://cds.cern.ch/record/1444880 |
Sumario: | The capability to perform extremely fast track reconstruction online is becoming more and more important for the LHC upgrade as well as the next generation of HEP experiments, where the expected instantaneous luminosities (in excess of 10^34 /cm2/s) and the very low signal/background ratio ask for fast and clean identification of the main characteristics of interesting events. The Slim5 R&D project studied different aspects of fast and high-precision tracking in dedicated hardware: data-push silicon sensors, high bandwidth DAQ systems and Associative Memories (AM) for fast track identification. The central element of the development system is a high traffic board, called EDRO, capable of collecting and processing digital data with an input rate of 16 Gbps. The input hits, suitably formatted or clusterized, are sent to an AM board sending back candidate tracks, which are identified at a rate of 40 MHz. The EDRO board is then able to deliver triggers and formatted events for further processing. The EDRO-AM system was first exploited on beam tests where it was able to process events at a maximum rate of 2.5 MHz, trigger events with identified tracks (maximum latency 1 us) and provide a clean sample of events with well reconstructed tracks. The flexibility of the EDRO-board design allows it to be coupled with completely different hit sources. In the ATLAS project called "Vertical Slice" the EDRO board receives level 1 triggered data from a part of the inner detector and, together with an AM board, identifies tracks for a possible use by the second level trigger processors. |
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