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Pulse Power Modulator development for the CLIC Damping Ring Kickers
The Compact Linear Collider (CLIC) study is exploring the scheme for an electron-positron collider with high luminosity (10-34 – 10-35 cm-2s-1) and a nominal centre-of-mass energy of 3 TeV: CLIC would complement LHC physics in the multi-TeV range. The CLIC design relies on Pre-Damping Rings (PDR) an...
Autores principales: | , |
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Lenguaje: | eng |
Publicado: |
2012
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Materias: | |
Acceso en línea: | http://cds.cern.ch/record/1448259 |
Sumario: | The Compact Linear Collider (CLIC) study is exploring the scheme for an electron-positron collider with high luminosity (10-34 – 10-35 cm-2s-1) and a nominal centre-of-mass energy of 3 TeV: CLIC would complement LHC physics in the multi-TeV range. The CLIC design relies on Pre-Damping Rings (PDR) and Damping Rings (DR) to achieve the very low emittance, through synchrotron radiation, needed for the luminosity requirements of CLIC. To limit the beam emittance blow-up due to oscillations, the pulse power modulators for the DR kickers must provide extremely flat, high-voltage pulses: the 2 GHz specification called for a 160 ns duration flat-top of 12.5 kV, 250 A, with a combined ripple and droop of not more than ±0.02 %. In order to meet these demanding specifications, a combination of broadband impedance matching, optimized electrical circuit layout and advanced control techniques is required. A solid-state modulator, the inductive adder, is the most promising approach to meeting the demanding specifications; this topology allows the use of both digital and analogue modulation. This report describes the preliminary design of the inductive adder and the use of active-filtering control algorithms for achieving the required pulse waveform. The report introduces the components of the inductive adder and presents equations and reasoning for selecting the main components: semiconductor switches, storage capacitors and transformer cores. Dimensioning of the adder stack structure is also covered, for achieving good impedance matching between the adder stack and the load. |
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