Cargando…
Upgraded readout electronics for the ATLAS LAr Calorimeter at the High Luminosity LHC
The ATLAS Liquid Argon (LAr) calorimeters produce a total of 182,486 signals which are digitized and processed by the front-end and back-end electronics at every triggered event. In addition, the front-end electronics is summing analog signals to provide coarsely grained energy sums, called trigger...
Autor principal: | |
---|---|
Lenguaje: | eng |
Publicado: |
2012
|
Materias: | |
Acceso en línea: | http://cds.cern.ch/record/1454247 |
Sumario: | The ATLAS Liquid Argon (LAr) calorimeters produce a total of 182,486 signals which are digitized and processed by the front-end and back-end electronics at every triggered event. In addition, the front-end electronics is summing analog signals to provide coarsely grained energy sums, called trigger towers, to the first-level trigger system, which is optimized for nominal LHC luminosities. However, the pile-up noise expected during the High Luminosity phases of LHC will be increased by factors of 3 to 7. An improved spatial granularity of the trigger primitives is therefore proposed in order to improve the identification performance for trigger signatures, like electrons or photons, at high background ejection rates. For the first upgrade phase [1] in 2018, new digital tower builder boards (sTBB) are being designed to receive higher granularity signals, digitize them on detector and send them via fast optical links to a new digital processing system (DPS). The DPS applies a digital filtering and identifies significant energy depositions in each trigger channel. The refined trigger primitives are then transmitted to the first level trigger system to extract improved trigger signatures. This talk will present the general concept of the upgraded LAr calorimeter readout together with the various electronics components to be developed for such a complex system. The R activities and architectural studies undertaken by the ATLAS LAr Calorimeter group will be described. Details of the on-going design of mixed-signal front-end ASICs, of radiation tolerant optical-links, and of the high-speed off-detector FPGA based DPS units will be presented. [1] ATLAS Collaboration, "Letter of Intent for the Phase-I Upgrade of the ATLAS Experiment", CERN-LHCC-2011-012. |
---|