The ATLAS IBL BOC Prototype Evaluation

In 2013 an additional layer, the Insertable B-Layer (IBL) will be added to the pixel detector of the ATLAS experiment at the LHC at CERN. For this fourth and innermost layer 448 newly developed pixel sensor readout chips (FE-I4) are used which will provide data from about 12 million pixel. For the readout of the IBL new off-detector electronic components are needed as the FE-I4s feature an increased readout bandwidth which can not be handled by the current system. To provide a degree of backward compatibility the new system will keep the structure of VME card pairs: The back of crate card (BOC) establishes the optical interfaces to the detector front end as well as to the read out system (ROS) while the read out driver (ROD) manages data processing and calibration. Both cards, the BOC and the ROD, have been redesigned and feature modern FPGA technology, yielding an integration four times higher than the current system. Regarding the new BOC this is achieved by replacing custom made optical and electrical (e.g. ASICs) components by commercial available ones and by integrating most of their functionalities into the FPGAs. Based on the first prototype we present details of the analysis of the design choices of the new BOC. The hardware components used to provide all the needed functionalities are tested and results will be shown. To evaluate commercial transmitter components versus the former used custom made ones, both have been placed on the prototype and comparisons can be done. The higher data rate and the support for a Fast TracKer system (FTK) made it necessary to implement the SLINK protocol, which is used to connect to the BOC to the ROS, into the FPGAs. For the optical connection Quad Small Form-factor Pluggable (QSFP) modules are evaluated as a substitute for the formerly used SFP transceivers. Furthermore the firmware blocks used to implement all needed tasks will be presented. Synchronization and 8b10b decoding is done for the incoming FE-I4 data stream (data from the previous FE-I3 chips is not encoded) and individual delay adjustment and BPM encoding is performed for the command channels to the detector front end in the Board Main FPGAs (BMF). The Board Control FPGA (BCF) is receiving control signals from the ROD via the VME backplane and is managing the configuration of the other two FPGAs and the PLL for the readout clock. Tests with the BOC prototype include communication tests with the new ROD prototype and first configuration and readout of an attached FE-I4 chip.