Topological and Central Trigger Processor for 2014 LHC luminosities

The ATLAS experiment is located at the European Center for Nu- clear Research (CERN) in Switzerland. It is designed to observe phe- nomena that involve highly massive particles produced in the collisions at the Large Hadron Collider (LHC): the world’s largest and highest-energy particle accelerator. Event triggering and Data Acquisition is one of the extraordinary challenges faced by the detectors at the high luminosity LHC collider. During 2011, the LHC reached instantaneous luminosities of 4×10^33 cm−1 s−1 and produced events with up to 24 interactions per colliding proton bunch. This places stringent operational and physical requirements on the AT- LAS Trigger in order to reduce the 40MHz collision rate to a manageable event storage rate of 400Hz and, at the same time, selecting those events considered interesting. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 75kHz and decision latency of less than 2.5μs. It is primarily composed of the Calorimeter Trigger, Muon Trigger, the Central Trigger Processor (CTP) and by 2014 a com- plete new electronics module: the Topological Processor (TP). With the TP will be possible for the first time to concentrate detailed information from subdetectors in a single Level-1 modules, determining angles between jets and/or leptons, or even more complex observables as muon isolation or invariant mass. Such TP information is provided to the CTP which time aligns the trigger inputs from different sources to the same bunch crossing and run algorithms to select an event on the basis of trigger menus. During the LHC shutdown in 2013 the TP and the upgraded CTP will be installed, this represent a major change in the final part of the Level-1 trigger chain. In this presentation the justification for such upgrade, the proposed CTP implementation to satisfy the requirements of the 2014 physics run at the LHC and the tests on the TP demonstrator and pro- totype with emphasis on the characterization of the high speed links and tests of topological algorithms in their firmware incarnation (latency and logic utilization), are illustrated.