The Upgrade of the PreProcessor System of the ATLAS Level-1 Calorimeter Trigger

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The ATLAS Level-1 Calorimeter Trigger is a pipelined system to identify high-pT objects and to build energy sums within a fixed latency of ~2 us. It consists of a PreProcessor, which conditions and digitises analogue calorimeter signals, and two object-finding processors. The PreProcessor's tas...

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Autor principal: Andrei, V
Lenguaje:eng
Publicado: 2012
Materias:
Detectors and Experimental Techniques
Acceso en línea:http://cds.cern.ch/record/1477973
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author Andrei, V
author_facet Andrei, V
author_sort Andrei, V
collection CERN
description The ATLAS Level-1 Calorimeter Trigger is a pipelined system to identify high-pT objects and to build energy sums within a fixed latency of ~2 us. It consists of a PreProcessor, which conditions and digitises analogue calorimeter signals, and two object-finding processors. The PreProcessor's tasks are implemented on a Multi-Chip Module, holding ADCs, time-adjustment and digital processing ASICs, and LVDS serialisers. A pin-compatible substitute, based on today's technology, like dual-channel ADCs and FPGAs, has been built to improve the BCID and pedestal subtraction algorithms. Test results with the first prototype are presented.
id cern-1477973
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2012
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spelling cern-14779732019-09-30T06:29:59Zhttp://cds.cern.ch/record/1477973engAndrei, VThe Upgrade of the PreProcessor System of the ATLAS Level-1 Calorimeter TriggerDetectors and Experimental TechniquesThe ATLAS Level-1 Calorimeter Trigger is a pipelined system to identify high-pT objects and to build energy sums within a fixed latency of ~2 us. It consists of a PreProcessor, which conditions and digitises analogue calorimeter signals, and two object-finding processors. The PreProcessor's tasks are implemented on a Multi-Chip Module, holding ADCs, time-adjustment and digital processing ASICs, and LVDS serialisers. A pin-compatible substitute, based on today's technology, like dual-channel ADCs and FPGAs, has been built to improve the BCID and pedestal subtraction algorithms. Test results with the first prototype are presented.ATL-DAQ-SLIDE-2012-520oai:cds.cern.ch:14779732012-09-14
spellingShingle Detectors and Experimental Techniques
Andrei, V
The Upgrade of the PreProcessor System of the ATLAS Level-1 Calorimeter Trigger
title The Upgrade of the PreProcessor System of the ATLAS Level-1 Calorimeter Trigger
title_full The Upgrade of the PreProcessor System of the ATLAS Level-1 Calorimeter Trigger
title_fullStr The Upgrade of the PreProcessor System of the ATLAS Level-1 Calorimeter Trigger
title_full_unstemmed The Upgrade of the PreProcessor System of the ATLAS Level-1 Calorimeter Trigger
title_short The Upgrade of the PreProcessor System of the ATLAS Level-1 Calorimeter Trigger
title_sort upgrade of the preprocessor system of the atlas level-1 calorimeter trigger
topic Detectors and Experimental Techniques
url http://cds.cern.ch/record/1477973
work_keys_str_mv AT andreiv theupgradeofthepreprocessorsystemoftheatlaslevel1calorimetertrigger
AT andreiv upgradeofthepreprocessorsystemoftheatlaslevel1calorimetertrigger

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