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Design through Verilog HDL
| Autores principales: | , |
|---|---|
| Lenguaje: | eng |
| Publicado: |
Wiley-IEEE Press
2004
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| Materias: | |
| Acceso en línea: | http://cds.cern.ch/record/1480681 |
| _version_ | 1780925867162075136 |
|---|---|
| author | Patman̲āpan̲, Ṭi Ār Tripura Sundari, B Bala |
| author_facet | Patman̲āpan̲, Ṭi Ār Tripura Sundari, B Bala |
| author_sort | Patman̲āpan̲, Ṭi Ār |
| collection | CERN |
| id | cern-1480681 |
| institution | Organización Europea para la Investigación Nuclear |
| language | eng |
| publishDate | 2004 |
| publisher | Wiley-IEEE Press |
| record_format | invenio |
| spelling | cern-14806812021-04-22T00:24:36Zhttp://cds.cern.ch/record/1480681engPatman̲āpan̲, Ṭi ĀrTripura Sundari, B BalaDesign through Verilog HDLEngineeringWiley-IEEE Pressoai:cds.cern.ch:14806812004 |
| spellingShingle | Engineering Patman̲āpan̲, Ṭi Ār Tripura Sundari, B Bala Design through Verilog HDL |
| title | Design through Verilog HDL |
| title_full | Design through Verilog HDL |
| title_fullStr | Design through Verilog HDL |
| title_full_unstemmed | Design through Verilog HDL |
| title_short | Design through Verilog HDL |
| title_sort | design through verilog hdl |
| topic | Engineering |
| url | http://cds.cern.ch/record/1480681 |
| work_keys_str_mv | AT patmanapantiar designthroughveriloghdl AT tripurasundaribbala designthroughveriloghdl |