Instrumentation of a Level-1 Track Trigger in the ATLAS detector for the High Luminosity LHC

One of the main challenges in particle physics experiments at hadron colliders is to build detector systems that can take advantage of the future luminosity increase that will take place during the next decade. More than 200 simultaneous collisions will be recorded in a single event which will make the task to extract the interesting physics signatures harder than ever before. Not all events can be recorded hence a fast trigger system is required to select events that will be stored for further analysis. In the ATLAS experiment at the Large Hadron Collider (LHC) two different architectures for accommodating a level-1 track trigger are being investigated. The tracker has more readout channels than can be readout in time for the trigger decision. Both architectures aim for a data reduction of 10-100 in order to make readout of data possible in time for a level-1 trigger decision. In the first architecture the data reduction is achieved by reading out only parts of the detector seeded by a high rate pre-trigger from the calorimeters and the muon system. An innovative double buffer is implemented in the front-end circuit. In the second architecture data reduction is achieved by correlating hits on closely spaced detector layers in the tracker. The offset between hits is a measure of the track momentum which open for data reduction by selecting only from high momentum tracks. A fast hit correlation logic is implemented on the detector modules. We describe the implementation of these schemes in the ATLAS tracker front-end electronics and the simulated performance of the system. Results on thresholds, rejection, bandwidth and trigger latency are shown and compared to the present requirements for the HL-LHC upgrade in ATLAS.