An FPGA based topological processor prototype for the ATLAS Level-1 trigger upgrade

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By 2014 the LHC will collide proton bunches at 14TeV with an increased instantaneous luminosity up to 3·10³⁴cm⁻²s⁻¹. The resulting higher event rate will challenge the existing ATLAS trigger system. A reduction on the trigger rate can be achieved by selecting interesting channels based on their expe...

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Detalles Bibliográficos
Autores principales: Bauss, B, Buescher, V, Degele, R, Ji, W, Moritz, S, Reiss, A, Schaefer, U, Simioni, E, Tapprogge, S, Wenzel, V
Lenguaje:eng
Publicado: 2012
Materias:
Detectors and Experimental Techniques
Acceso en línea:http://cds.cern.ch/record/1490584

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