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Guide to FPGA Implementation of Arithmetic Functions
This book is designed both for FPGA users interested in developing new, specific components - generally for reducing execution times –and IP core designers interested in extending their catalog of specific components. The main focus is circuit synthesis and the discussion shows, for example, how a...
Autores principales: | , , |
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Lenguaje: | eng |
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Springer
2012
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Materias: | |
Acceso en línea: | https://dx.doi.org/10.1007/978-94-007-2987-2 http://cds.cern.ch/record/1501910 |
_version_ | 1780927087939420160 |
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author | Deschamps, Jean-Pierre Sutter, Gustavo D Cantó, Enrique |
author_facet | Deschamps, Jean-Pierre Sutter, Gustavo D Cantó, Enrique |
author_sort | Deschamps, Jean-Pierre |
collection | CERN |
description | This book is designed both for FPGA users interested in developing new, specific components - generally for reducing execution times –and IP core designers interested in extending their catalog of specific components. The main focus is circuit synthesis and the discussion shows, for example, how a given algorithm executing some complex function can be translated to a synthesizable circuit description, as well as which are the best choices the designer can make to reduce the circuit cost, latency, or power consumption. This is not a book on algorithms. It is a book that shows how to translate efficiently an algorithm to a circuit, using techniques such as parallelism, pipeline, loop unrolling, and others. Numerous examples of FPGA implementation are described throughout this book and the circuits are modeled in VHDL. Complete and synthesizable source files are available for download. |
id | cern-1501910 |
institution | Organización Europea para la Investigación Nuclear |
language | eng |
publishDate | 2012 |
publisher | Springer |
record_format | invenio |
spelling | cern-15019102021-04-21T23:55:16Zdoi:10.1007/978-94-007-2987-2http://cds.cern.ch/record/1501910engDeschamps, Jean-PierreSutter, Gustavo DCantó, EnriqueGuide to FPGA Implementation of Arithmetic FunctionsEngineeringThis book is designed both for FPGA users interested in developing new, specific components - generally for reducing execution times –and IP core designers interested in extending their catalog of specific components. The main focus is circuit synthesis and the discussion shows, for example, how a given algorithm executing some complex function can be translated to a synthesizable circuit description, as well as which are the best choices the designer can make to reduce the circuit cost, latency, or power consumption. This is not a book on algorithms. It is a book that shows how to translate efficiently an algorithm to a circuit, using techniques such as parallelism, pipeline, loop unrolling, and others. Numerous examples of FPGA implementation are described throughout this book and the circuits are modeled in VHDL. Complete and synthesizable source files are available for download.Springeroai:cds.cern.ch:15019102012 |
spellingShingle | Engineering Deschamps, Jean-Pierre Sutter, Gustavo D Cantó, Enrique Guide to FPGA Implementation of Arithmetic Functions |
title | Guide to FPGA Implementation of Arithmetic Functions |
title_full | Guide to FPGA Implementation of Arithmetic Functions |
title_fullStr | Guide to FPGA Implementation of Arithmetic Functions |
title_full_unstemmed | Guide to FPGA Implementation of Arithmetic Functions |
title_short | Guide to FPGA Implementation of Arithmetic Functions |
title_sort | guide to fpga implementation of arithmetic functions |
topic | Engineering |
url | https://dx.doi.org/10.1007/978-94-007-2987-2 http://cds.cern.ch/record/1501910 |
work_keys_str_mv | AT deschampsjeanpierre guidetofpgaimplementationofarithmeticfunctions AT suttergustavod guidetofpgaimplementationofarithmeticfunctions AT cantoenrique guidetofpgaimplementationofarithmeticfunctions |