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Error Control for Network-on-Chip Links
As technology scales into nanoscale regime, it is impossible to guarantee the perfect hardware design. Moreover, if the requirement of 100% correctness in hardware can be relaxed, the cost of manufacturing, verification, and testing will be significantly reduced. Many approaches have been proposed t...
| Autores principales: | , |
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| Lenguaje: | eng |
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Springer
2012
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| Acceso en línea: | https://dx.doi.org/10.1007/978-1-4419-9313-7 http://cds.cern.ch/record/1503622 |