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Heterogeneous Multicore Processor Technologies for Embedded Systems

To satisfy the higher requirements of digitally converged embedded systems, this book describes heterogeneous multicore technology that uses various kinds of low-power embedded processor cores on a single chip. With this technology, heterogeneous parallelism can be implemented on an SoC, and greater...

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Detalles Bibliográficos
Autores principales: Uchiyama, Kunio, Arakawa, Fumio, Kasahara, Hironori, Nojiri, Tohru, Noda, Hideyuki, Tawara, Yasuhiro, Idehara, Akio, Iwata, Kenichi, Shikano, Hiroaki
Lenguaje:eng
Publicado: Springer 2012
Materias:
Acceso en línea:https://dx.doi.org/10.1007/978-1-4614-0284-8
http://cds.cern.ch/record/1503702
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author Uchiyama, Kunio
Arakawa, Fumio
Kasahara, Hironori
Nojiri, Tohru
Noda, Hideyuki
Tawara, Yasuhiro
Idehara, Akio
Iwata, Kenichi
Shikano, Hiroaki
author_facet Uchiyama, Kunio
Arakawa, Fumio
Kasahara, Hironori
Nojiri, Tohru
Noda, Hideyuki
Tawara, Yasuhiro
Idehara, Akio
Iwata, Kenichi
Shikano, Hiroaki
author_sort Uchiyama, Kunio
collection CERN
description To satisfy the higher requirements of digitally converged embedded systems, this book describes heterogeneous multicore technology that uses various kinds of low-power embedded processor cores on a single chip. With this technology, heterogeneous parallelism can be implemented on an SoC, and greater flexibility and superior performance per watt can then be achieved. This book defines the heterogeneous multicore architecture and explains in detail several embedded processor cores including CPU cores and special-purpose processor cores that achieve highly arithmetic-level parallelism. The authors developed three multicore chips (called RP-1, RP-2, and RP-X) according to the defined architecture with the introduced processor cores. The chip implementations, software environments, and applications running on the chips are also explained in the book. Provides readers an overview and practical discussion of heterogeneous multicore technologies from both a hardware and software point of view; Discusses a new, high-performance and energy efficient approach to designing SoCs for digitally converged, embedded systems; Covers hardware issues such as architecture and chip implementation, as well as software issues such as compilers, operating systems, and application programs; Describes three chips developed according to the defined heterogeneous multicore architecture, including chip implementations, software environments, and working applications.
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institution Organización Europea para la Investigación Nuclear
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publishDate 2012
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spelling cern-15037022021-04-21T23:54:03Zdoi:10.1007/978-1-4614-0284-8http://cds.cern.ch/record/1503702engUchiyama, KunioArakawa, FumioKasahara, HironoriNojiri, TohruNoda, HideyukiTawara, YasuhiroIdehara, AkioIwata, KenichiShikano, HiroakiHeterogeneous Multicore Processor Technologies for Embedded SystemsEngineeringTo satisfy the higher requirements of digitally converged embedded systems, this book describes heterogeneous multicore technology that uses various kinds of low-power embedded processor cores on a single chip. With this technology, heterogeneous parallelism can be implemented on an SoC, and greater flexibility and superior performance per watt can then be achieved. This book defines the heterogeneous multicore architecture and explains in detail several embedded processor cores including CPU cores and special-purpose processor cores that achieve highly arithmetic-level parallelism. The authors developed three multicore chips (called RP-1, RP-2, and RP-X) according to the defined architecture with the introduced processor cores. The chip implementations, software environments, and applications running on the chips are also explained in the book. Provides readers an overview and practical discussion of heterogeneous multicore technologies from both a hardware and software point of view; Discusses a new, high-performance and energy efficient approach to designing SoCs for digitally converged, embedded systems; Covers hardware issues such as architecture and chip implementation, as well as software issues such as compilers, operating systems, and application programs; Describes three chips developed according to the defined heterogeneous multicore architecture, including chip implementations, software environments, and working applications.Springeroai:cds.cern.ch:15037022012
spellingShingle Engineering
Uchiyama, Kunio
Arakawa, Fumio
Kasahara, Hironori
Nojiri, Tohru
Noda, Hideyuki
Tawara, Yasuhiro
Idehara, Akio
Iwata, Kenichi
Shikano, Hiroaki
Heterogeneous Multicore Processor Technologies for Embedded Systems
title Heterogeneous Multicore Processor Technologies for Embedded Systems
title_full Heterogeneous Multicore Processor Technologies for Embedded Systems
title_fullStr Heterogeneous Multicore Processor Technologies for Embedded Systems
title_full_unstemmed Heterogeneous Multicore Processor Technologies for Embedded Systems
title_short Heterogeneous Multicore Processor Technologies for Embedded Systems
title_sort heterogeneous multicore processor technologies for embedded systems
topic Engineering
url https://dx.doi.org/10.1007/978-1-4614-0284-8
http://cds.cern.ch/record/1503702
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