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Verilog HDL: a guide to digital design and synthesis
| Autor principal: | |
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| Lenguaje: | eng |
| Publicado: |
SunSoft Press
2003
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| Materias: | |
| Acceso en línea: | http://cds.cern.ch/record/1505487 |
| _version_ | 1780927268028153856 |
|---|---|
| author | Palnitkar, Samir |
| author_facet | Palnitkar, Samir |
| author_sort | Palnitkar, Samir |
| collection | CERN |
| id | cern-1505487 |
| institution | Organización Europea para la Investigación Nuclear |
| language | eng |
| publishDate | 2003 |
| publisher | SunSoft Press |
| record_format | invenio |
| spelling | cern-15054872021-04-21T23:51:51Zhttp://cds.cern.ch/record/1505487engPalnitkar, SamirVerilog HDL: a guide to digital design and synthesisEngineeringSunSoft Pressoai:cds.cern.ch:15054872003 |
| spellingShingle | Engineering Palnitkar, Samir Verilog HDL: a guide to digital design and synthesis |
| title | Verilog HDL: a guide to digital design and synthesis |
| title_full | Verilog HDL: a guide to digital design and synthesis |
| title_fullStr | Verilog HDL: a guide to digital design and synthesis |
| title_full_unstemmed | Verilog HDL: a guide to digital design and synthesis |
| title_short | Verilog HDL: a guide to digital design and synthesis |
| title_sort | verilog hdl: a guide to digital design and synthesis |
| topic | Engineering |
| url | http://cds.cern.ch/record/1505487 |
| work_keys_str_mv | AT palnitkarsamir veriloghdlaguidetodigitaldesignandsynthesis |