Cargando…
Design and characteristics of a 32-channel, 100 MHz, zero suppressing, FASTBUS pulse shape digitizer
Autores principales: | Bourgeois, F, Corre, A, Friedrich, D, Marcelin, J P, Mildner, G, Schaile, O, Von Walter, P, Weber, C |
---|---|
Lenguaje: | eng |
Publicado: |
1984
|
Materias: | |
Acceso en línea: | http://cds.cern.ch/record/155134 |
Ejemplares similares
-
A 15 MHz 32-channel flash ADC FASTBUS board for use at LEP
por: Crawley, H B, et al.
Publicado: (1987) -
Results of a 100 MHz FADC system built in Fastbus used by the UA2 vertex detector
por: Bourgeois, F, et al.
Publicado: (1986) -
High-density CAMAC and FASTBUS charge integrating ADC for use at the LEP OPAL detector
por: Bourgeois, F, et al.
Publicado: (1986) -
MIMOSA: a 32-channel 40 MHz CAMAC scaler
por: Beer, Arno Siegfried, et al.
Publicado: (1981) -
The XOP processor in FASTBUS
por: Lecoq, J, et al.
Publicado: (1985)