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Verilog coding for logic synthesis
| Autor principal: | |
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| Lenguaje: | eng |
| Publicado: |
Wiley-Interscience
2003
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| Materias: | |
| Acceso en línea: | http://cds.cern.ch/record/1555060 |
| _version_ | 1780930385952112640 |
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| author | Lee, Weng Fook |
| author_facet | Lee, Weng Fook |
| author_sort | Lee, Weng Fook |
| collection | CERN |
| id | cern-1555060 |
| institution | Organización Europea para la Investigación Nuclear |
| language | eng |
| publishDate | 2003 |
| publisher | Wiley-Interscience |
| record_format | invenio |
| spelling | cern-15550602021-04-21T22:39:15Zhttp://cds.cern.ch/record/1555060engLee, Weng FookVerilog coding for logic synthesisComputing and ComputersWiley-Interscienceoai:cds.cern.ch:15550602003 |
| spellingShingle | Computing and Computers Lee, Weng Fook Verilog coding for logic synthesis |
| title | Verilog coding for logic synthesis |
| title_full | Verilog coding for logic synthesis |
| title_fullStr | Verilog coding for logic synthesis |
| title_full_unstemmed | Verilog coding for logic synthesis |
| title_short | Verilog coding for logic synthesis |
| title_sort | verilog coding for logic synthesis |
| topic | Computing and Computers |
| url | http://cds.cern.ch/record/1555060 |
| work_keys_str_mv | AT leewengfook verilogcodingforlogicsynthesis |