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Constraining designs for synthesis and timing analysis: a practical guide to synopsys design constraints (SDC)
This book serves as a hands-on guide to timing constraints in integrated circuit design. Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly. Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis...
| Autores principales: | , |
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| Lenguaje: | eng |
| Publicado: |
Springer
2013
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| Acceso en línea: | https://dx.doi.org/10.1007/978-1-4614-3269-2 http://cds.cern.ch/record/1555606 |