Highly Integrated Mixed-Mode Electronics for the readout of Time Projection Chambers

Time Projection Chambers (TPCs) are one of the most prevalent particle trackers for high-energy physics experiments. Future planed TPCs for the International Linear Collider (ILC) and the Compact Linear Collider (CLIC) entail very high spatial resolution in large gas volumes, but impose low material budget for the end caps of the TPC cylinder. This constraint is not accomplished with the state-of-the-art front-end electronics because of its unsuited relatively large mass and of its associated water cooling system. To reach the required material budget, highly compact and power efficient dedicated TPC front-end electronics should be developed. This project aims at re-designing the different electronic elements with significant improvements in terms of performance, power efficiency and versatility, and developing an integrated circuit that merges all components of the front-end electronics. This chip ambitions a large volume production at low unitary cost and its employment in multiple detectors. The design of an analog-to-digital converter (ADC) tailored for this application is necessary and also the most challenging task, because of its circuit complexity and great impact on the overall front-end electronics performance. The modern submicron CMOS technology offers specific mechanisms for decoupling between different domains. However, the integration of low noise amplifiers with digital circuits has not been previously attempted for this application. Besides, the CMOS technology advances entail the reduction of the power supply voltages, which brings new challenges to the design of ADCs and analog circuits in general. The channel architecture of the proposed chip is based on the front-end electronics employed at the TPC of the ALICE experiment, of the Large Hadron Collider that operates at the European Organization for Nuclear Research (CERN). It is implemented in two Application Specific Integrated Circuits (ASICs), one completely analog and the other mixed-mode. These ASICs are implemented in CMOS processes of 0.35μm and 0.25μm, and operate with 3.3V and 2.5V power supplies. The first element of the readout chain is the analog block that consists of a charge sensitive amplifier and shaper. In the circuit specifically developed for this project, the gain and the peaking time are programmable. The tuneable capabilities of this circuit make it suitable for most TPC’s geometries, amplification of ionization technologies, gas types and voltage settings. It was prototyped standalone and successfully tested on a 16-channel chip named PCA16. The second element of the readout chain, which is a 10-bit 40MS/s ADC, was also designed and prototyped separately, in a 2-channel chip. It was implemented in a pipelined architecture with eight 1.5-bit stages and one 2-bit stage. Its power efficiency was enhanced, when compared to the conventional pipelined implementation, by the use of switched-capacitor double sampling structures. This technique, allowed reducing greatly the power consumption of the ADC’s internal operational amplifiers. Various innovative ideas were combined with established circuit techniques to achieve good performance parameters, low power consumption and a small silicon area, coping at the same time with the low supply voltage of the 0.13μm CMOS technology. The final element of the readout chain is the digital block. It consists of a sequence of functions, whose main objective is to reduce the data volume without removing any pertinent information. The data reduction algorithm is based on a simple zero suppression principle, however, its efficiency is highly constrained by the performance of the precedent digital functions. These are the baseline correction and tail cancellation filter units, which condition the complex shapes of the input signals. Having as starting point the digital algorithms from the ALTRO chip used in the ALICE TPC, the digital block was redesigned and implemented in the more recent 0.13μm CMOS technology. A 16-channel ASIC that integrates the complete TPC readout chain was designed and produced. This chip was named S-ALTRO Demonstrator and merged the charge amplifier and the ADC prototyped separately beforehand, and the digital processing unit. This chip proved the technical feasibility of integrating on the same piece of silicon the complete analog and digital electronics required for the TPC readout. It offers an unprecedented power efficiency and compactness of the full TPC readout front-end electronics. Each channel occupies an area of only 3mm2 of silicon, which is below the minimum expected pad area foreseen for the future coming TPCs. This small area brings optimism to the concept of mounting the front-end cards in parallel to the TPC’s readout plane. The S-ALTRO Demonstrator represents a significant technological progress of the front-end electronics for TPC readout. It also provides a larger degree of flexibility for covering most of the technological options of the upcoming TPCs.