ATLAS Central Trigger Processor Input Module (CTPIN) Firmware Upgrade

The upgraded CTPIN firmware is designed to receive its inputs at twice the design speed. A constraint is that the CTPIN hardware will not be changed, so the upgrade is constrained to the firmware of the Pipeline FPGA and the Monitoring FPGA. The Pipeline FPGA is configured to latch in DDR registers the 32 XSDP input signals at 80 MHz and then decode and latch them internally in 64 registers operating at 40 MHz. After synchronization and alignment these 64 trigger signals are encoded and exported in 31 output lines, using Double-Data-Rate (DDR) registers. Again in the Monitoring module the 31 input trigger signals are decoded and latched in 62 internal signals, using DDR registers. The Pipeline FPGA and Monitoring FPGA firmware have been successfully verified in timing simulation, which shows that an upgrade of the CTPIN without redesigning the hardware is feasible.