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ATLAS Central Trigger Processor Input Module (CTPIN) Firmware Upgrade
The upgraded CTPIN firmware is designed to receive its inputs at twice the design speed. A constraint is that the CTPIN hardware will not be changed, so the upgrade is constrained to the firmware of the Pipeline FPGA and the Monitoring FPGA. The Pipeline FPGA is configured to latch in DDR registers...
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| Lenguaje: | eng |
| Publicado: |
2013
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| Acceso en línea: | http://cds.cern.ch/record/1596055 |