Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench

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The portable test bench (VME based) used for the certification of the Tile calorimeter front-end electronics has been redesigned for the LHC Long Shutdown (2013-2014) improving its portability. The new version is based on a Xilinx Virtex 5 FPGA that implements an embedded system using a hard core Po...

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Autores principales: Carrio, F, Kim, H Y, Moreno, P, Reed, R, Sandrock, C, Shalyugin, A, Schettino, V, Solans, C, Souza, J, Usai, G, Valero, A
Lenguaje:eng
Publicado: 2013
Materias:
Detectors and Experimental Techniques
Acceso en línea:http://cds.cern.ch/record/1601997
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author Carrio, F
Kim, H Y
Moreno, P
Reed, R
Sandrock, C
Shalyugin, A
Schettino, V
Solans, C
Souza, J
Usai, G
Valero, A
author_facet Carrio, F
Kim, H Y
Moreno, P
Reed, R
Sandrock, C
Shalyugin, A
Schettino, V
Solans, C
Souza, J
Usai, G
Valero, A
author_sort Carrio, F
collection CERN
description The portable test bench (VME based) used for the certification of the Tile calorimeter front-end electronics has been redesigned for the LHC Long Shutdown (2013-2014) improving its portability. The new version is based on a Xilinx Virtex 5 FPGA that implements an embedded system using a hard core PowerPC 440 microprocessor and custom IP cores. The PowerPC microprocessor runs a light Linux version and handles the IP cores written in VHDL that implement the different functionalities (TTC, G-Link, CAN-Bus) Description of the system and performance measurements of the different components will be shown.
id cern-1601997
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2013
record_format invenio
spelling cern-16019972019-09-30T06:29:59Zhttp://cds.cern.ch/record/1601997engCarrio, FKim, H YMoreno, PReed, RSandrock, CShalyugin, ASchettino, VSolans, CSouza, JUsai, GValero, ADesign of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-benchDetectors and Experimental TechniquesThe portable test bench (VME based) used for the certification of the Tile calorimeter front-end electronics has been redesigned for the LHC Long Shutdown (2013-2014) improving its portability. The new version is based on a Xilinx Virtex 5 FPGA that implements an embedded system using a hard core PowerPC 440 microprocessor and custom IP cores. The PowerPC microprocessor runs a light Linux version and handles the IP cores written in VHDL that implement the different functionalities (TTC, G-Link, CAN-Bus) Description of the system and performance measurements of the different components will be shown.ATL-TILECAL-SLIDE-2013-631oai:cds.cern.ch:16019972013-09-19
spellingShingle Detectors and Experimental Techniques
Carrio, F
Kim, H Y
Moreno, P
Reed, R
Sandrock, C
Shalyugin, A
Schettino, V
Solans, C
Souza, J
Usai, G
Valero, A
Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench
title Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench
title_full Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench
title_fullStr Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench
title_full_unstemmed Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench
title_short Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench
title_sort design of an fpga-based embedded system for the atlas tile calorimeter front-end electronics test-bench
topic Detectors and Experimental Techniques
url http://cds.cern.ch/record/1601997
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