Upgrade of the Trigger Readout System of the ATLAS Liquid Argon Calorimeters

The ATLAS detector was designed and built to study proton-proton collisions produced at the LHC at centre-of-mass energies up to 14 TeV and instantaneous luminosities up to 10^34 cm^-2 s^-1. Liquid argon (LAr) sampling calorimeters are employed for all electromagnetic calorimetry in the pseudorapidity region |eta|<3.2, and for hadronic calorimetry in the region from |eta|=1.5 to |eta|=4.9. The ATLAS Liquid Argon (LAr) calorimeters produce a total of 182,486 signals which are digitizedand processed by the front-end and back-end electronics at every triggered event. In addition, the front-end electronics sums analog signals to provide coarsely grained energy sums, called trigger towers, to the first-level trigger system, which is optimized for nominal LHC luminosities. In 2018, an instantaneous luminosity of 2-3 x 10^34 cm^-2 s^-1 is expected, far beyond the nominal one for which the detector was designed. In order to cope with this increased trigger rate, an improved spatial granularity of the trigger primitives is proposed in order to improve the identification performance for trigger signatures, like electrons, photons, tau leptons, jets, total and missing energy, at high background rejection rates. For these purposes, a new LAr Trigger Digitizer Board (LTDB) is being designed to receive higher granularity signals, digitize them on detector and send them via fast optical links to a new digital processing system (DPS). The DPS applies a digital filtering and identifies significant energy depositions in each trigger channel. The refined trigger primitives are then transmitted to the first level trigger system to extract improved trigger signatures. This talk will present the general concept of the upgraded LAr calorimeter trigger together with the various electronics components to be developed for such a complex system. The R&D activities as well as architectural and performance studies undertaken by the ATLAS LAr Calorimeter group will bedescribed. Details of the on-going design of mixed-signal front-end ASICs, of radiation tolerant optical-links, and of the high-speed off-detector FPGA based DPS units will be presented.