Novel Front-end Electronics for Time Projection Chamber Detectors

This work has been carried out in the European Organization for Nuclear Research (CERN) and it was supported by the European Union as part of the research and development towards the European detector the (EUDET) project, specifically for the International Linear Collider (ILC). In particle physics there are several different categories of particle detectors. The presented design is focused on a particular kind of tracking detector called Time Projection Chamber (TPC). The TPC provides a three dimensional image of electrically charged particles crossing a gaseous volume. The thesis includes a study of the requirements for future TPC detectors summarizing the parameters that the front-end readout electronics must fulfill. In addition, these requirements are compared with respect to the readouts used in existing TPC detectors. It is concluded that none of the existing front-end readout designs fulfill the stringent requirements. The main requirements for future TPC detectors are high integration, an increased number of channels, faster electronics and very low power. The principal disadvantage of existing readout systems is the utilization of several integrated circuits in the acquisition chain. Those systems cannot achieve the high integration needed for future detectors. In addition, the increase in the number of channels and sampling rate planned for future detectors would increase the power consumption in the existing systems above the acceptable values. In consequence, it would also increase the loading on the necessary cooling systems. This thesis presents the integration of the whole acquisition chain (analog front-end filters, analog-to-digital converter (ADC) and digital signal processing) into a single integrated circuit in 130nm CMOS technology. This chip is the first that contains such a high integration level for TPC applications. Another area of importance which has been researched is the detailed analysis of the digital processing filters, and these results are presented here. The most important objectives are the reduction of power consumption in the digital processing blocks and reduction of digital noise. Finally, this thesis shows the 16-channel prototype which has provided very satisfactory test results. The integration success has been quantified by measuring the crosstalk (0.3 %) and the absence of digital noise in the ADC sampling. In addition, the digital power consumption has been reduced to 28 % of the preceding design. Moreover, the concept of one of the most important power reduction techniques, power pulsing, has been proven. The power has been reduced from 47.25mW/channel to 1.76mW/channel with a duty cycle of 0.5 %. Future investigation lines will focus on the design of a 64-channel integrated circuit based on the topology proven in this thesis.