An 8-channel programmable 80/160/320 Mbit/s radiation-hard phase-aligner circuit in 130-nm CMOS

The design of an 8-channel phase-aligner which is part of the GBTX chip for the LHC upgrade program is presented. The circuit is able to align the phases of up to 8 serial data streams to the GBTX transmitter clock so that the data can be merged, serialized and transmitted to the counting room. The bit rate is programmable at 80, 160 or 320Mbit/s. Data jitter up to +-3 T(bit)/8 can be tolerated without jeopardizing the error-free data reception. The phase-aligner has been designed as a radiation-hard circuit in a 130nm CMOS technology and consumes only 3.5mW at a supply voltage of 1.5V.