An 8-channel programmable 80/160/320 Mbit/s radiation-hard phase-aligner circuit in 130-nm CMOS

The design of an 8-channel phase-aligner which is part of the GBTX chip for the LHC upgrade program is presented. The circuit is able to align the phases of up to 8 serial data streams to the GBTX transmitter clock so that the data can be merged, serialized and transmitted to the counting room. The...

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Detalles Bibliográficos
Autores principales: Tavernier, F, Bonacini, S, Moreira, P
Lenguaje:eng
Publicado: 2012
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1088/1748-0221/7/12/C12022
http://cds.cern.ch/record/1608682
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author Tavernier, F
Bonacini, S
Moreira, P
author_facet Tavernier, F
Bonacini, S
Moreira, P
author_sort Tavernier, F
collection CERN
description The design of an 8-channel phase-aligner which is part of the GBTX chip for the LHC upgrade program is presented. The circuit is able to align the phases of up to 8 serial data streams to the GBTX transmitter clock so that the data can be merged, serialized and transmitted to the counting room. The bit rate is programmable at 80, 160 or 320Mbit/s. Data jitter up to +-3 T(bit)/8 can be tolerated without jeopardizing the error-free data reception. The phase-aligner has been designed as a radiation-hard circuit in a 130nm CMOS technology and consumes only 3.5mW at a supply voltage of 1.5V.
id cern-1608682
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2012
record_format invenio
spelling cern-16086822019-09-30T06:29:59Zdoi:10.1088/1748-0221/7/12/C12022http://cds.cern.ch/record/1608682engTavernier, FBonacini, SMoreira, PAn 8-channel programmable 80/160/320 Mbit/s radiation-hard phase-aligner circuit in 130-nm CMOSDetectors and Experimental TechniquesThe design of an 8-channel phase-aligner which is part of the GBTX chip for the LHC upgrade program is presented. The circuit is able to align the phases of up to 8 serial data streams to the GBTX transmitter clock so that the data can be merged, serialized and transmitted to the counting room. The bit rate is programmable at 80, 160 or 320Mbit/s. Data jitter up to +-3 T(bit)/8 can be tolerated without jeopardizing the error-free data reception. The phase-aligner has been designed as a radiation-hard circuit in a 130nm CMOS technology and consumes only 3.5mW at a supply voltage of 1.5V.oai:cds.cern.ch:16086822012
spellingShingle Detectors and Experimental Techniques
Tavernier, F
Bonacini, S
Moreira, P
An 8-channel programmable 80/160/320 Mbit/s radiation-hard phase-aligner circuit in 130-nm CMOS
title An 8-channel programmable 80/160/320 Mbit/s radiation-hard phase-aligner circuit in 130-nm CMOS
title_full An 8-channel programmable 80/160/320 Mbit/s radiation-hard phase-aligner circuit in 130-nm CMOS
title_fullStr An 8-channel programmable 80/160/320 Mbit/s radiation-hard phase-aligner circuit in 130-nm CMOS
title_full_unstemmed An 8-channel programmable 80/160/320 Mbit/s radiation-hard phase-aligner circuit in 130-nm CMOS
title_short An 8-channel programmable 80/160/320 Mbit/s radiation-hard phase-aligner circuit in 130-nm CMOS
title_sort 8-channel programmable 80/160/320 mbit/s radiation-hard phase-aligner circuit in 130-nm cmos
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.1088/1748-0221/7/12/C12022
http://cds.cern.ch/record/1608682
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AT tavernierf 8channelprogrammable80160320mbitsradiationhardphasealignercircuitin130nmcmos
AT bonacinis 8channelprogrammable80160320mbitsradiationhardphasealignercircuitin130nmcmos
AT moreirap 8channelprogrammable80160320mbitsradiationhardphasealignercircuitin130nmcmos

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