Variable resolution pattern generation for the Associative Memory of the ATLAS FTK project

The Associative Memory (AM) chip is special device that allows to find coincidence patterns, or just patterns, between the incoming data in up to 8 parallel streams. The latest AM chip has been designed to receive silicon clusters generated in 8 layers of the ATLAS silicon detector sensor, to perform parallel track pattern matching at high rate and it will be the core of the FTK project. Data going through each of the busses are compared with a bank of patterns and AM chip looks for matches in each line, like commercial content addressable memory (CAM). The high density of hits expected in the ATLAS inner detector from 2015 put a challenge in the capability of the AM chip in rejecting random coincidences, requiring either an extremely high number of high precision patterns, with increasing costs and complexity of the system, or more flexible solutions. For this reason in the most recent prototype of the AM chip ternary cells have been added in the logic, allowing “don’t care” (DC) bits in the match. Having DC-bits in the least significant bits of the match allows to change the precision of the match, varying the resolution of the match for each pattern and each detector layer. In order to tune the use of the DC-bits we have carried out detailed simulation studies to define: 1) the best procedure to build the pattern bank and set the DC bits to obtain the best rejection of random coincidences without loss in efficiency 2) the best precision that satisfies the hardware constraints with the expected pileup conditions. We will present the result we have obtained and methods we have developed to train and generate the pattern bank and setup the DC-bits content up to 3 bits, showing how this affects the system performance in terms of dataflow within the system and efficiency in the track reconstruction. We will also present preliminary results for new ideas that in the future will allow to use more DC-bits.