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Digital VLSI design with Verilog: a textbook from Silicon Valley Technical Institute
This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project. In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,0...
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| Lenguaje: | eng |
| Publicado: |
Springer
2008
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| Acceso en línea: | http://cds.cern.ch/record/1621148 |
| _version_ | 1780933179614429184 |
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| author | Williams, John |
| author_facet | Williams, John |
| author_sort | Williams, John |
| collection | CERN |
| description | This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project. In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs. Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided on the |
| id | cern-1621148 |
| institution | Organización Europea para la Investigación Nuclear |
| language | eng |
| publishDate | 2008 |
| publisher | Springer |
| record_format | invenio |
| spelling | cern-16211482021-04-21T21:51:31Zhttp://cds.cern.ch/record/1621148engWilliams, JohnDigital VLSI design with Verilog: a textbook from Silicon Valley Technical InstituteEngineeringThis unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project. In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs. Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided on theSpringeroai:cds.cern.ch:16211482008 |
| spellingShingle | Engineering Williams, John Digital VLSI design with Verilog: a textbook from Silicon Valley Technical Institute |
| title | Digital VLSI design with Verilog: a textbook from Silicon Valley Technical Institute |
| title_full | Digital VLSI design with Verilog: a textbook from Silicon Valley Technical Institute |
| title_fullStr | Digital VLSI design with Verilog: a textbook from Silicon Valley Technical Institute |
| title_full_unstemmed | Digital VLSI design with Verilog: a textbook from Silicon Valley Technical Institute |
| title_short | Digital VLSI design with Verilog: a textbook from Silicon Valley Technical Institute |
| title_sort | digital vlsi design with verilog: a textbook from silicon valley technical institute |
| topic | Engineering |
| url | http://cds.cern.ch/record/1621148 |
| work_keys_str_mv | AT williamsjohn digitalvlsidesignwithverilogatextbookfromsiliconvalleytechnicalinstitute |