Hardware and firmware developments for the upgrade of the ATLAS Level-1 Central Trigger Processor

The Central Trigger Processor (CTP) is the final stage of the ATLAS first level trigger system which reduces the collision rate of 40 MHz to a Level-1 event rate of 100 kHz. An upgrade of the CTP is currently underway to significantly increase the number of trigger inputs and trigger combinations, a...

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Autores principales: Anders, G, Bertelsen, H, Boisen, A, Childers, T, Dam, M, Ellis, N, Farthouat, P, Gabaldon Ruiz, C, Ghibaudi, M, Gorini, B, Haas, S, Kaneda, M, Ohm, C, Silva Oliveira, M, Pauly, T, Pottgen, R, Schmieden, K, Spiwoks, R, Xella, S
Lenguaje:eng
Publicado: 2013
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1088/1748-0221/9/01/C01035
http://cds.cern.ch/record/1623812
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author Anders, G
Bertelsen, H
Boisen, A
Childers, T
Dam, M
Ellis, N
Farthouat, P
Gabaldon Ruiz, C
Ghibaudi, M
Gorini, B
Haas, S
Kaneda, M
Ohm, C
Silva Oliveira, M
Pauly, T
Pottgen, R
Schmieden, K
Spiwoks, R
Xella, S
author_facet Anders, G
Bertelsen, H
Boisen, A
Childers, T
Dam, M
Ellis, N
Farthouat, P
Gabaldon Ruiz, C
Ghibaudi, M
Gorini, B
Haas, S
Kaneda, M
Ohm, C
Silva Oliveira, M
Pauly, T
Pottgen, R
Schmieden, K
Spiwoks, R
Xella, S
author_sort Anders, G
collection CERN
description The Central Trigger Processor (CTP) is the final stage of the ATLAS first level trigger system which reduces the collision rate of 40 MHz to a Level-1 event rate of 100 kHz. An upgrade of the CTP is currently underway to significantly increase the number of trigger inputs and trigger combinations, allowing additional flexibility for the trigger menu. We present the hardware and FPGA firmware of the newly designed core module (CTPCORE+) module of the CTP, as well as results from a system used for early firmware and software prototyping based on commercial FPGA evaluation boards. First test result from the CTPCORE+ module will also be shown.
id cern-1623812
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2013
record_format invenio
spelling cern-16238122022-08-10T20:26:22Zdoi:10.1088/1748-0221/9/01/C01035http://cds.cern.ch/record/1623812engAnders, GBertelsen, HBoisen, AChilders, TDam, MEllis, NFarthouat, PGabaldon Ruiz, CGhibaudi, MGorini, BHaas, SKaneda, MOhm, CSilva Oliveira, MPauly, TPottgen, RSchmieden, KSpiwoks, RXella, SHardware and firmware developments for the upgrade of the ATLAS Level-1 Central Trigger ProcessorDetectors and Experimental TechniquesThe Central Trigger Processor (CTP) is the final stage of the ATLAS first level trigger system which reduces the collision rate of 40 MHz to a Level-1 event rate of 100 kHz. An upgrade of the CTP is currently underway to significantly increase the number of trigger inputs and trigger combinations, allowing additional flexibility for the trigger menu. We present the hardware and FPGA firmware of the newly designed core module (CTPCORE+) module of the CTP, as well as results from a system used for early firmware and software prototyping based on commercial FPGA evaluation boards. First test result from the CTPCORE+ module will also be shown.ATL-DAQ-PROC-2013-035oai:cds.cern.ch:16238122013-11-02
spellingShingle Detectors and Experimental Techniques
Anders, G
Bertelsen, H
Boisen, A
Childers, T
Dam, M
Ellis, N
Farthouat, P
Gabaldon Ruiz, C
Ghibaudi, M
Gorini, B
Haas, S
Kaneda, M
Ohm, C
Silva Oliveira, M
Pauly, T
Pottgen, R
Schmieden, K
Spiwoks, R
Xella, S
Hardware and firmware developments for the upgrade of the ATLAS Level-1 Central Trigger Processor
title Hardware and firmware developments for the upgrade of the ATLAS Level-1 Central Trigger Processor
title_full Hardware and firmware developments for the upgrade of the ATLAS Level-1 Central Trigger Processor
title_fullStr Hardware and firmware developments for the upgrade of the ATLAS Level-1 Central Trigger Processor
title_full_unstemmed Hardware and firmware developments for the upgrade of the ATLAS Level-1 Central Trigger Processor
title_short Hardware and firmware developments for the upgrade of the ATLAS Level-1 Central Trigger Processor
title_sort hardware and firmware developments for the upgrade of the atlas level-1 central trigger processor
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.1088/1748-0221/9/01/C01035
http://cds.cern.ch/record/1623812
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