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High performance multi-channel high-speed I/O circuits
This book describes design techniques that can be used to mitigate crosstalk in high-speed I/O circuits. The focus of the book is in developing compact and low power integrated circuits for crosstalk cancellation, inter-symbol interference (ISI) mitigation and improved bit error rates (BER) at highe...
Autores principales: | , |
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Lenguaje: | eng |
Publicado: |
Springer
2013
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Materias: | |
Acceso en línea: | https://dx.doi.org/10.1007/978-1-4614-4963-8 http://cds.cern.ch/record/1625587 |
_version_ | 1780933663461998592 |
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author | Oh, Taehyoun Harjani, Ramesh |
author_facet | Oh, Taehyoun Harjani, Ramesh |
author_sort | Oh, Taehyoun |
collection | CERN |
description | This book describes design techniques that can be used to mitigate crosstalk in high-speed I/O circuits. The focus of the book is in developing compact and low power integrated circuits for crosstalk cancellation, inter-symbol interference (ISI) mitigation and improved bit error rates (BER) at higher speeds. This book is one of the first to discuss in detail the problem of crosstalk and ISI mitigation encountered as data rates have continued beyond 10Gb/s. Readers will learn to avoid the data performance cliff, with circuits and design techniques described for novel, low power crosstalk cancel |
id | cern-1625587 |
institution | Organización Europea para la Investigación Nuclear |
language | eng |
publishDate | 2013 |
publisher | Springer |
record_format | invenio |
spelling | cern-16255872021-04-21T21:41:49Zdoi:10.1007/978-1-4614-4963-8http://cds.cern.ch/record/1625587engOh, TaehyounHarjani, RameshHigh performance multi-channel high-speed I/O circuitsEngineeringThis book describes design techniques that can be used to mitigate crosstalk in high-speed I/O circuits. The focus of the book is in developing compact and low power integrated circuits for crosstalk cancellation, inter-symbol interference (ISI) mitigation and improved bit error rates (BER) at higher speeds. This book is one of the first to discuss in detail the problem of crosstalk and ISI mitigation encountered as data rates have continued beyond 10Gb/s. Readers will learn to avoid the data performance cliff, with circuits and design techniques described for novel, low power crosstalk cancelSpringeroai:cds.cern.ch:16255872013 |
spellingShingle | Engineering Oh, Taehyoun Harjani, Ramesh High performance multi-channel high-speed I/O circuits |
title | High performance multi-channel high-speed I/O circuits |
title_full | High performance multi-channel high-speed I/O circuits |
title_fullStr | High performance multi-channel high-speed I/O circuits |
title_full_unstemmed | High performance multi-channel high-speed I/O circuits |
title_short | High performance multi-channel high-speed I/O circuits |
title_sort | high performance multi-channel high-speed i/o circuits |
topic | Engineering |
url | https://dx.doi.org/10.1007/978-1-4614-4963-8 http://cds.cern.ch/record/1625587 |
work_keys_str_mv | AT ohtaehyoun highperformancemultichannelhighspeediocircuits AT harjaniramesh highperformancemultichannelhighspeediocircuits |