Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench

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The portable test-bench for the certification of the ATLAS tile hadronic calorimeter front-end electronics has been redesigned for the LHC Long Shutdown (LS1) improving its portability and expanding its functionalities. This paper presents a new test-bench based on a Xilinx Virtex-5 FPGA that implem...

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Autores principales: Carrio, F, Kim, H Y, Moreno, P, Reed, R, Sandrock, C, Shalyugin, A, Schettino, V, Souza, J, Solans, C, Usai, G, Valero, A
Lenguaje:eng
Publicado: 2013
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1088/1748-0221/9/03/C03023
http://cds.cern.ch/record/1627588
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author Carrio, F
Kim, H Y
Moreno, P
Reed, R
Sandrock, C
Shalyugin, A
Schettino, V
Souza, J
Solans, C
Usai, G
Valero, A
author_facet Carrio, F
Kim, H Y
Moreno, P
Reed, R
Sandrock, C
Shalyugin, A
Schettino, V
Souza, J
Solans, C
Usai, G
Valero, A
author_sort Carrio, F
collection CERN
description The portable test-bench for the certification of the ATLAS tile hadronic calorimeter front-end electronics has been redesigned for the LHC Long Shutdown (LS1) improving its portability and expanding its functionalities. This paper presents a new test-bench based on a Xilinx Virtex-5 FPGA that implements an embedded system using a hard core PowerPC 440 microprocessor and custom IP cores. A light Linux version runs on the PowerPC microprocessor and handles the IP cores which implement the different functionalities as TTCvi emulation, G-Link decoder ADC control and data reception, needed to perform the desired tests
id cern-1627588
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2013
record_format invenio
spelling cern-16275882022-08-10T20:48:23Zdoi:10.1088/1748-0221/9/03/C03023http://cds.cern.ch/record/1627588engCarrio, FKim, H YMoreno, PReed, RSandrock, CShalyugin, ASchettino, VSouza, JSolans, CUsai, GValero, ADesign of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-benchDetectors and Experimental TechniquesThe portable test-bench for the certification of the ATLAS tile hadronic calorimeter front-end electronics has been redesigned for the LHC Long Shutdown (LS1) improving its portability and expanding its functionalities. This paper presents a new test-bench based on a Xilinx Virtex-5 FPGA that implements an embedded system using a hard core PowerPC 440 microprocessor and custom IP cores. A light Linux version runs on the PowerPC microprocessor and handles the IP cores which implement the different functionalities as TTCvi emulation, G-Link decoder ADC control and data reception, needed to perform the desired testsATL-TILECAL-PROC-2013-017oai:cds.cern.ch:16275882013-11-12
spellingShingle Detectors and Experimental Techniques
Carrio, F
Kim, H Y
Moreno, P
Reed, R
Sandrock, C
Shalyugin, A
Schettino, V
Souza, J
Solans, C
Usai, G
Valero, A
Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench
title Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench
title_full Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench
title_fullStr Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench
title_full_unstemmed Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench
title_short Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench
title_sort design of an fpga-based embedded system for the atlas tile calorimeter front-end electronics test-bench
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.1088/1748-0221/9/03/C03023
http://cds.cern.ch/record/1627588
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