Upgrade of the ATLAS Level-1 trigger with an FPGA based Topological Processor

The ATLAS experiment is located at the European Centre for Nuclear Research (CERN) in Switzerland. It is designed to measure decay properties of high energetic particles produced in the protons collisions at the Large Hadron Collider (LHC). The LHC has a proton collision at a frequency of 40 MHz, and thus requires a trigger system to efficiently select events down to a manageable event storage rate of about 400Hz. Event triggering is therefore one of the extraordinary challenges faced by the ATLAS detector. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 75kHz and decision latency of less than 2.5$\mu$s. It is primarily composed of the Calorimeter Trigger, Muon Trigger, the Central Trigger Processor (CTP). Due to the increase in the LHC instantaneous luminosity up to 3$\times$10$^{34}$ cm$^{−2}$ s$^{−1}$ from 2015 onwards, a new element will be included in the Level-1 Trigger scheme: the Topological Processor (L1Topo). The L1Topo receives data in a dedicated format from the calorimeters and muon detectors to be processed into specific topological algorithms. Those algorithms sit in high-end FPGAs which perform geometrical cuts, correlations and calculate complex observables such as the invariant mass. The output of such topological algorithms is sent to the CTP. Since the Level-1 trigger is a fixed latency pipelined system, the main requirements for the L1Topo are a large input bandwidth ($\approx$1Tb/s), optical connectivity and low processing latency on the Real Time data path. This presentation focuses on the design of the L1Topo final production module and the tests results on L1Topo prototypes. Such tests are aimed at characterizing high-speed links (signal integrity, bit error rate, margin analysis and latency) plus algorithms logic resource utilization.