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A radiation-hard PLL for frequency multiplication with programmable input clock and phase-selectable output signals in 130 nm CMOS
A PLL (ePLL) is presented that is intended to be used as a frequency multiplier. The ePLL accepts 40, 80, 160 or 320 MHz as a reference and generates clocks at the same frequencies, regardless of the input clock. Moreover, the outputs are available with a phase resolution of 90 degrees for the 40, 8...
Autores principales: | , , |
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Lenguaje: | eng |
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2012
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Acceso en línea: | https://dx.doi.org/10.1088/1748-0221/7/12/C12014 http://cds.cern.ch/record/1629557 |
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author | Poltorak, K Moreira, P Tavernier, F |
author_facet | Poltorak, K Moreira, P Tavernier, F |
author_sort | Poltorak, K |
collection | CERN |
description | A PLL (ePLL) is presented that is intended to be used as a frequency multiplier. The ePLL accepts 40, 80, 160 or 320 MHz as a reference and generates clocks at the same frequencies, regardless of the input clock. Moreover, the outputs are available with a phase resolution of 90 degrees for the 40, 80 and 160 MHz output and 22.5 degrees for the 320 MHz output. The radiation-hard design, integrated in a 130 nm CMOS technology, is able to operate at a supply voltage between 1.2V and 1.5V. |
id | cern-1629557 |
institution | Organización Europea para la Investigación Nuclear |
language | eng |
publishDate | 2012 |
record_format | invenio |
spelling | cern-16295572019-09-30T06:29:59Zdoi:10.1088/1748-0221/7/12/C12014http://cds.cern.ch/record/1629557engPoltorak, KMoreira, PTavernier, FA radiation-hard PLL for frequency multiplication with programmable input clock and phase-selectable output signals in 130 nm CMOSDetectors and Experimental TechniquesA PLL (ePLL) is presented that is intended to be used as a frequency multiplier. The ePLL accepts 40, 80, 160 or 320 MHz as a reference and generates clocks at the same frequencies, regardless of the input clock. Moreover, the outputs are available with a phase resolution of 90 degrees for the 40, 80 and 160 MHz output and 22.5 degrees for the 320 MHz output. The radiation-hard design, integrated in a 130 nm CMOS technology, is able to operate at a supply voltage between 1.2V and 1.5V.oai:cds.cern.ch:16295572012 |
spellingShingle | Detectors and Experimental Techniques Poltorak, K Moreira, P Tavernier, F A radiation-hard PLL for frequency multiplication with programmable input clock and phase-selectable output signals in 130 nm CMOS |
title | A radiation-hard PLL for frequency multiplication with programmable input clock and phase-selectable output signals in 130 nm CMOS |
title_full | A radiation-hard PLL for frequency multiplication with programmable input clock and phase-selectable output signals in 130 nm CMOS |
title_fullStr | A radiation-hard PLL for frequency multiplication with programmable input clock and phase-selectable output signals in 130 nm CMOS |
title_full_unstemmed | A radiation-hard PLL for frequency multiplication with programmable input clock and phase-selectable output signals in 130 nm CMOS |
title_short | A radiation-hard PLL for frequency multiplication with programmable input clock and phase-selectable output signals in 130 nm CMOS |
title_sort | radiation-hard pll for frequency multiplication with programmable input clock and phase-selectable output signals in 130 nm cmos |
topic | Detectors and Experimental Techniques |
url | https://dx.doi.org/10.1088/1748-0221/7/12/C12014 http://cds.cern.ch/record/1629557 |
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