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A radiation-hard PLL for frequency multiplication with programmable input clock and phase-selectable output signals in 130 nm CMOS
A PLL (ePLL) is presented that is intended to be used as a frequency multiplier. The ePLL accepts 40, 80, 160 or 320 MHz as a reference and generates clocks at the same frequencies, regardless of the input clock. Moreover, the outputs are available with a phase resolution of 90 degrees for the 40, 8...
| Autores principales: | , , |
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| Lenguaje: | eng |
| Publicado: |
2012
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.1088/1748-0221/7/12/C12014 http://cds.cern.ch/record/1629557 |