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Methods for the Application of Programmable Logic Devices in Electronic Protection Systems for High Energy Particle Accelerators

The present thesis was realised within the framework of the Doctoral Student programme at the European Organisation for Nuclear Research CERN, which is situated near Geneva. The aim of this thesis was to develop a method for reliable firmware implementation and to use that method to implement a new...

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Autor principal: Kwiatkowski, Maciej
Lenguaje:eng
Publicado: 2013
Materias:
Acceso en línea:http://cds.cern.ch/record/1632194
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author Kwiatkowski, Maciej
author_facet Kwiatkowski, Maciej
author_sort Kwiatkowski, Maciej
collection CERN
description The present thesis was realised within the framework of the Doctoral Student programme at the European Organisation for Nuclear Research CERN, which is situated near Geneva. The aim of this thesis was to develop a method for reliable firmware implementation and to use that method to implement a new firmware for the Safe Machine Parameters (SMP) system. That system relies heavily on the Field Programmable Gate Arrays (FPGA) and it is one of the key machine protection systems of the Large Hadron Collider (LHC). The conception of the SMP hardware originates from the fully tested Beam Interlock System (BIS) being a result of another PhD thesis. For that reason the reliable SMP hardware was preserved unchanged. The first version of the SMP was ready for the LHC startup in the year 2008. Nevertheless the quality of the SMP firmware was objectionable. There were new requirements and therefore the SMP specification was extended. On that occasion it was decided that the existing SMP firmware will not be continued and that it should be started from scratch. For the new version the firmware implementation should be carried out on the basis of the strictly defined approach, which will ensure high quality and therefore reliability of the SMP. The starting point of the work was the IEC~61508 standard, which was supposed to be matched for the specific needs of the facility carrying out the high energy physics experiments like CERN. As the result of that thesis a full electronic protection system lifecycle was proposed, form the conception through the risk analysis to the implementation and deployment. The method proposed was applied to the critical firmware implementation of the SMP. Examples of the most critical functions realised by the SMP system are shown in the final chapters of the thesis. The second version of the SMP was deployed to be used in the LHC accelerator in the year 2010. Since then it performs its role without failures and therefore it is foreseen to be operated without any changes up to the end of the LHC project. The second result of the thesis is the proposed lifecycle, which can be used for the evaluation of the existing project or for the implementation of the new programmable protection systems for the high energy particle experiments at CERN or in the similar scientific laboratory.
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institution Organización Europea para la Investigación Nuclear
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spelling cern-16321942019-09-30T06:29:59Zhttp://cds.cern.ch/record/1632194engKwiatkowski, MaciejMethods for the Application of Programmable Logic Devices in Electronic Protection Systems for High Energy Particle AcceleratorsEngineeringComputing and ComputersAccelerators and Storage RingsThe present thesis was realised within the framework of the Doctoral Student programme at the European Organisation for Nuclear Research CERN, which is situated near Geneva. The aim of this thesis was to develop a method for reliable firmware implementation and to use that method to implement a new firmware for the Safe Machine Parameters (SMP) system. That system relies heavily on the Field Programmable Gate Arrays (FPGA) and it is one of the key machine protection systems of the Large Hadron Collider (LHC). The conception of the SMP hardware originates from the fully tested Beam Interlock System (BIS) being a result of another PhD thesis. For that reason the reliable SMP hardware was preserved unchanged. The first version of the SMP was ready for the LHC startup in the year 2008. Nevertheless the quality of the SMP firmware was objectionable. There were new requirements and therefore the SMP specification was extended. On that occasion it was decided that the existing SMP firmware will not be continued and that it should be started from scratch. For the new version the firmware implementation should be carried out on the basis of the strictly defined approach, which will ensure high quality and therefore reliability of the SMP. The starting point of the work was the IEC~61508 standard, which was supposed to be matched for the specific needs of the facility carrying out the high energy physics experiments like CERN. As the result of that thesis a full electronic protection system lifecycle was proposed, form the conception through the risk analysis to the implementation and deployment. The method proposed was applied to the critical firmware implementation of the SMP. Examples of the most critical functions realised by the SMP system are shown in the final chapters of the thesis. The second version of the SMP was deployed to be used in the LHC accelerator in the year 2010. Since then it performs its role without failures and therefore it is foreseen to be operated without any changes up to the end of the LHC project. The second result of the thesis is the proposed lifecycle, which can be used for the evaluation of the existing project or for the implementation of the new programmable protection systems for the high energy particle experiments at CERN or in the similar scientific laboratory.CERN-THESIS-2013-216oai:cds.cern.ch:16321942013-11-28T22:28:54Z
spellingShingle Engineering
Computing and Computers
Accelerators and Storage Rings
Kwiatkowski, Maciej
Methods for the Application of Programmable Logic Devices in Electronic Protection Systems for High Energy Particle Accelerators
title Methods for the Application of Programmable Logic Devices in Electronic Protection Systems for High Energy Particle Accelerators
title_full Methods for the Application of Programmable Logic Devices in Electronic Protection Systems for High Energy Particle Accelerators
title_fullStr Methods for the Application of Programmable Logic Devices in Electronic Protection Systems for High Energy Particle Accelerators
title_full_unstemmed Methods for the Application of Programmable Logic Devices in Electronic Protection Systems for High Energy Particle Accelerators
title_short Methods for the Application of Programmable Logic Devices in Electronic Protection Systems for High Energy Particle Accelerators
title_sort methods for the application of programmable logic devices in electronic protection systems for high energy particle accelerators
topic Engineering
Computing and Computers
Accelerators and Storage Rings
url http://cds.cern.ch/record/1632194
work_keys_str_mv AT kwiatkowskimaciej methodsfortheapplicationofprogrammablelogicdevicesinelectronicprotectionsystemsforhighenergyparticleaccelerators