Control Logic for the Interlock system of the ATLAS Insertable B-Layer

Part of the first upgrade program of the ATLAS detector is the installation of the Insertable B-Layer (IBL) as a fourth and innermost detector layer of the ATLAS pixel detector to prepare the tracking system for the expected increase of pile-up events. As with every sub-detector, the IBL and its components have to be monitored and controlled via a Detector Control System (DCS). A hardware-based interlock system is installed on-site to prevent detector and people working at the detector from serious harm and damage. For the IBL, the logical processing of interlock signals is realised in Interlock Matrix Crates (IMCs) using Complex Programmable Logic Devices (CPLD). One part of this master thesis is the automatic implementation of the logical assignments from database information. A script was developed to generate the needed file to program the CPLD. The second part of this thesis is the design of a test setup to verify the functionality of the electrical components of each IMC and to confirm the correct processing of interlock signals in the CPLD. The test setup was built and programmed successfully to verify electrical functionality and logical processing. Simultaneously, the setup was used to test the general design of IMC components during prototyping and to test IMCs during the beginning of their production.