Through Silicon Via Redistribution of I/O Pads

An 80x80 pixel ASIC for connection to CdTe detectors for spectroscopic X-ray imaging has been designed at the Rutherford Appleton Laboratory. The 20mm x 21.4mm ASIC is intrinsically 3-side butt-able when bump bonded to a 20mm x 20mm detector. The 4th edge has readout structures and the input/output (110) pads for wire bonding. This necessitates 3mm of inactive space between detectors on this edge when the detectors are tiled together. To reduce this lost space we have redistributed the 110 pads through the ASIC silicon substrate to the back of the ASIC and wire bonded on the back of the module. This wafer level technology step performed by Tohoku-MicroTec Co. Ltd. allows much greater area coverage for modular solid state detectors. The paper describes the process and results from first 8inch wafers of devices