A Highly Parallel FPGA Implementation of a 2D-Clustering Algorithm for the ATLAS Fast TracKer (FTK) Processor

The highly parallel 2D-clustering FPGA implementation used for the input system of Fast TracKer (FTK) processor for the ATLAS experiment at Large Hadron Collider (LHC) at CERN is presented. The LHC after the 2013-2014 shutdown periods is expected to increase the luminosity, which will make more difficult to have efficient online selection of rare events due to the increasing of the overlapping collisions. FTK is highly-parallelized hardware system that allows improving online selection by real time track finding using silicon inner detector information. FTK system require Fast and robust clustering of hits position from silicon detector on FPGA. We show the development of original input boards and implemented clustering algorithm. For the complicated 2D-clustering, moving window technique is used to minimize the limited FPGA resources. Developed boards and implementation of the clustering algorithm has sufficient processing power to meet the specification for silicon inner detector of ATLAS for the maximum LHC luminosity planned until 2022. And developed algorithm is easily adjustable to other image processing applications which require real-time 2D-clustering.