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A Hardware Track Trigger (FTK) for the ATLAS Trigger
The design and studies of the performance for the ATLAS hardware Fast TracKer (FTK) are presented. The existing trigger system of the ATLAS experiment is deployed to reduce the event rate from the bunch crossing rate of 40 MHz to < 1 KHz for permanent storage at the LHC design luminosity of 10^34...
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Lenguaje: | eng |
Publicado: |
2014
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Materias: | |
Acceso en línea: | http://cds.cern.ch/record/1703521 |
Sumario: | The design and studies of the performance for the ATLAS hardware Fast TracKer (FTK) are presented. The existing trigger system of the ATLAS experiment is deployed to reduce the event rate from the bunch crossing rate of 40 MHz to < 1 KHz for permanent storage at the LHC design luminosity of 10^34 cm^-2 s^-1. The LHC has performed exceptionally well and routinely exceeds the design luminosity and from 2015 is due to operate with higher still luminosities. This will place a significant load on the High Level trigger (HLT) system, both due to the need for more sophisticated algorithms to reject background, and from the larger data volumes that will need to be processed. The Fast TracKer is a custom electronics system that will operate at the full Level-1 accepted rate of 100 KHz and provide high quality tracks at the beginning of processing in the HLT. This will be performing by track reconstruction using hardware with massive parallelism using associative memories (AM) and FPGAs. The availability of the full tracking information will ensure robust HLT selection within the affordable latency available at the HLT, with only a limited degradation in performance arising from the additional pileup from higher luminosity running. The parallel system architecture is presented, with a focus on the I/O interfaces which use Advanced Telecommunications Computing Architecture (ATCA) technology to handle the massive data volumes from the ATLAS silicon detector, and the data output to the HLT. The processing units incorporate more than 8000 AM chips to store and match ~ 10^9 patterns, and more than 1000 FPGAs to perform data formatting and track fitting. The latest R&D progress for the individual components is discussed, including the design and prototyping of the next generation AM chip and the custom ATCA blades. The results from in-situ test results are also presented. The performance in important physics areas is demonstrated using the ATLAS Monte Carlo simulation at different LHC luminosities. |
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