LHCb: F.E.C. for DAQ networks

The demand for faster and more reliable networks is growing day by day both in commercial and scientific applications, driving many innovations in network protocols, fiber optics and network-controllers. Operating fast links on relatively inexpensive hardware is a very important challenging aspect of this. One important way to enable this is to provide the network with an existing mechanism of error correction, called Forward Error Correction (F.E.C.). Although error-correcting codes exist for over six decades and F.E.C. is applied in various projects, it is still not widespread in Ethernet networks. F.E.C. introduces a very cost effective way to expand the limits of any network based on micro-controllers synthesized on FPGAs, but it is provided only for specific applications, such as backplane systems. Most of the FPGA and/or IP core vendors either do not provide this feature on their Ethernet implementations or their F.E.C. implementations are based on Ethernet micro-controllers that have a different structure that the IEEE 802.3-2008 standard describes. The benefits from F.E.C. apply not only on bandwidth rates but also in the total cost of the network equipment. F.E.C. provides a better way, in terms of efficiency, to submit data, as it allows the correction of packets containing errors without adding any protocol overhead, thus expanding the bandwidth limit without any further changes to the network. On the other hand F.E.C. can cut down costs of fibre optics or transceivers. It can provide a low Bit Error Rate for a low cost manufacturing fibre optics network, which can be even or better with a network based on more expensive equipment without the F.E.C.. The most important elements of the Ethernet stack for the F.E.C. are the PCS (Physical Coding Sub-layer) and the PMA (Physical Medium Attachment). F.E.C. is placed between the PCS and the PMA and it is designed to provide error correction while being invisible to the rest of the micro-controller. This means that it does not require any driver or IP core updates/optimizations to work. In this paper we present the key elements of the F.E.C. following the IEEE 802.3-2008 standard. We will describe the mathematical aspects of our implementation. On the technical point we will analyze the key elements of the F.E.C. and we will provide the implementation steps. We will provide measurements on each element about throughput, max operating frequency and the changes that have to be made to adapt it to any vendors IP.