The eCDR, a Radiation-Hard 40/80/160/320 Mbit/s CDR with internal VCO frequency calibration and 195 ps programmable phase resolution in 130 nm CMOS

A clock and data recovery IP, the eCDR, is presented which is intended to be implemented on the detector front-end ASICs that need to communicate with the GBTX by means of e-links. The programmable CDR accepts data at 40, 80, 160 or 320Mbit/s and generates retimed data as well as 40, 80, 160 and 320MHz clocks that are aligned to the retimed data. Moreover, all the outputs have a programmable phase with a resolution of 195ps. An internal calibration mechanism enables the eCDR to lock on incoming data even without the availability of any form of reference clock. The radiation-hard design, integrated in a 130nm CMOS technology, operates at a supply voltage between 1.2V and 1.5V. The power consumption is between 28.5mW and 34.5mW, depending on the settings. The eCDR can achieve a very low RMS jitter below 10ps.